This invention is in the field of integrated circuit packages and packaging methods.
The demand for a reduction in size and an increase in complexity and performance of electronic components has driven the industry to produce smaller and more complex integrated circuits (ICs). These same trends have forced the development of IC packages having small footprints, high lead counts, and better electrical and thermal performance. At the same time, these IC packages are required to meet accepted industry standards. Power dissipation is a particular challenge since higher performance ICs produce more thermal energy, and the smaller packages of today allow the designer few options through which to dissipate this energy. For a typical flip-chip integrated circuit, the primary means for removing heat from the package is from the backside of the chip (the front side being mounted face-down on a substrate). Unfortunately, the chip is relatively fragile and easily broken, so it is difficult to mount a relatively heavy heatsink to the chip's backside without causing damage. Another problem is that the chip is usually much smaller than a heatsink of the size required for the appropriate amount of thermal dissipation. This makes the mounting of the heatsink even more difficult, the reason being that the interface between the chip and heatsink must be carefully controlled in order to obtain high thermal performance, and a large heatsink is difficult to mount precisely on a relatively small chip. Ideally, the interface would be as thin and uniform as possible. The industry refers to the thermal interface as a “bond line”, and the thickness and uniformity of the bond line is considered key to the successful manufacture of a high performance integrated circuit package.
In the traditional prior art approach to the problem of dissipating heat from an IC, shown in FIG. 1, a ceramic ball grid array package is fitted with a copper-tungsten lid that serves both as a thermal sink as well as to protect the integrated circuit. The chip 100 is mounted face-down on a ceramic substrate 110 with solder bumps 120. Underfill 130 protects the active surface of the chip and strengthens the chip-to-substrate attachment. Thermally conductive compound 140 is compressed between the chip backside and the inner surface of lid 150. Lid 150 is attached to substrate 110 with adhesive 160. Solder balls 170 connect the assembly to the next level of interconnection, such as a printed circuit board. While this packaging technology has been used for some time in industry, it suffers from various disadvantages, including poor thermal performance as a result of the difficulties involved in obtaining precise bond line characteristics. These difficulties arise from the fact that the lid itself as well as the techniques used to mounted the lid to the substrate are relatively imprecise. For example, the lid is difficult to fabricate to a high degree of precision at an economical cost, and the adhesive 160 used to attach the lid to the substrate can be inconsistent in thickness. These and other factors can result in the lid being tilted or rotated relative to the chip, which can result in poor bond line characteristics.
A second prior art approach, shown in FIG. 2, overcomes some of the disadvantages of the FIG. 1 package. This direct lid attach package again includes a chip 200 mounted face-down on a substrate 210 with solder bumps 220. Underfill 230 is inserted between chip and substrate as above. However, instead of a lid sealed to the substrate, lid 250 is only attached to the backside of chip 200. The sole mechanical support for the lid is a thermally-conductive adhesive 240. The package is completed by solder balls 270 on the bottom of the substrate. An advantage of this approach is that the relatively simple lid can be attached more efficiently and at lower cost than in the traditional approach shown in FIG. 1.
While the technology shown in FIG. 2 solves some of the problems inherent in the traditional approach, it still suffers from disadvantages. In particular, the mechanical integrity of the lid to chip interface is questionable in view of the limited area over which the bond occurs relative to the lid and chip size. The thermally-conductive adhesive necessary to support the lid is also expensive and is considered exotic by many in the industry. The primary disadvantage of the direct-lid-attach approach, however, is that precise mounting of the lid to the chip is difficult. The tendency of the lid to tilt or rotate during mounting results in a bond line between the chip and lid that is too thin in places and too thick elsewhere. This is particularly a problem for large chip sizes and when a relatively heavy heatsink (rather than a lid) is attached directly to the chip backside. Such non-uniformity in the bond line results is less than optimal thermal performance of the interface. It is therefore apparent that a need exists in the industry for an improved package and packaging method for products that benefit from efficient thermal dissipation.